1. Field of the Invention
The present invention relates to a shift register employing a transistor, and particularly, relates to a shift register for controlling a display device.
2. Description of the Related Art
In display devices employing light emitting elements of a self-luminous type typified by an organic light emitting diode (OLED which is also called an organic EL element, an electroluminescence element, or the like) and liquid crystal display devices, a circuit for driving pixels is formed over the same substrate as the pixels. In such a circuit, a signal to sequentially select a plurality of wirings, a plurality of circuits (e.g., switches), or the like is required to be generated, therefore, a shift register is employed in many cases.
A shift register is generally supplied with clock signals, and operates in synchronization with the clock signals. However, the clock signal is supplied to all unit registers constituting the shift register, so that a large load is applied to a wiring for supplying the clock signal, which results in large power consumption.
It is to be noted here that a unit register corresponds to circuits for one stage or several stages in a shift register. A plurality of the unit registers are connected in series to constitute a shift register.
A technology has been proposed in which a clock signal is selectively supplied only to the unit register at the stage whose data is a level of significance (e.g., an H signal in the case of the positive logic). (e.g., see Patent Document 1)
[Patent Document 1] Japanese Patent No. 3326691
FIG. 19 is a circuit diagram of a unit register described in Patent Document 1. An input signal and an output signal of a delay flip-flop circuit (DFF) are inputted into a NOR circuit 1903. In the case where both of the input signal and the output signal are L signals, a transfer gate (also called an analog switch) 1901 and a transfer gate 1902 are both turned OFF simultaneously so that clock signals CLK1 and CLK2 are not supplied to the DFF. In the case where at least one of the input signal and the output signal is an H signal, the transfer gate 1901 and the transfer gate 1902 are both turned ON simultaneously so that the clock signals CLK1 and CLK2 are provided to the DFF.
Note that a specific circuit diagram of the DFF is shown in FIG. 20.
Next, another circuit described in Patent Document 1 is shown in FIG. 21. In FIG. 21, a transfer gate 2101 and a transfer gate 2102 are respectively constituted only by transistors having one polarity. Accordingly, no NOR circuit is required unlike the circuit shown in FIG. 19. In the case where one of the input signal and the output signal of the DFF is an L signal, the transfer gate 2101 and the transfer gate 2102 are both turned OFF simultaneously. Furthermore, in the case where at least one of the input signal and the output signal of the DFF is an H signal, the transfer gate 2101 and the transfer gate 2102 are both turned OFF simultaneously.
In the case of Patent Document 1, the transfer gates 1901 and 1902, and the transfer gates 2101 and 2102 are respectively turned ON simultaneously, so that a clock signal supply is controlled simultaneously. Consequently, a large load is applied to a wiring for supplying the clock signal, which results in large power consumption.
Furthermore, the circuit shown in FIG. 19 where the NOR circuit 1903 is provided is complex. On the other hand, no NOR circuit is provided in FIG. 21. However, in the circuit shown in FIG. 21, voltage is decreased for threshold voltage in the transfer gates 2101 and 2102 as described in Patent Document 1. Therefore, the amplitude of a clock signal is decreased to be supplied to the DFF. Accordingly, a transistor to turn OFF is not turned OFF, which leads to malfunction. In addition, current continues to flow in the transistor which is not turned OFF, so that power consumption is increased.